<html><body><samp><pre>
<!@TC:1471512135>
#Build: Synplify Pro J-2015.03L-SP1, Build 123R, Aug 18 2015
#install: C:\lscc\diamond\3.6_x64\synpbase
#OS: Windows 7 6.1
#Hostname: CNLW7BJNICK

#Implementation: syn_results

<a name=compilerReport1></a>Synopsys HDL Compiler, version comp201503sp1p1, Build 117R, built Aug 18 2015</a>
@N: : <!@TM:1471512135> | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

<a name=compilerReport2></a>Synopsys Verilog Compiler, version comp201503sp1p1, Build 117R, built Aug 18 2015</a>
@N: : <!@TM:1471512135> | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@I::"C:\lscc\diamond\3.6_x64\synpbase\lib\lucent\ecp5u.v"
@I::"C:\lscc\diamond\3.6_x64\synpbase\lib\lucent\pmi_def.v"
@I::"C:\lscc\diamond\3.6_x64\synpbase\lib\vlog\hypermods.v"
@I::"C:\lscc\diamond\3.6_x64\synpbase\lib\vlog\umr_capim.v"
@I::"C:\lscc\diamond\3.6_x64\synpbase\lib\vlog\scemi_objects.v"
@I::"C:\lscc\diamond\3.6_x64\synpbase\lib\vlog\scemi_pipes.svh"
@I::"C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\ecp5u.v"
@I::"C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\pmi_def.v"
@I::"D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v"
@N:<a href="@N:CG346:@XP_HELP">CG346</a> : <a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:143:36:143:45:@N:CG346:@XP_MSG">ip_gddr71tx.v(143)</a><!@TM:1471512135> | Read full_case directive 
@N:<a href="@N:CG347:@XP_HELP">CG347</a> : <a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:143:46:143:59:@N:CG347:@XP_MSG">ip_gddr71tx.v(143)</a><!@TM:1471512135> | Read parallel_case directive 
<font color=#A52A2A>@W:<a href="@W:CG286:@XP_HELP">CG286</a> : <a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:143:2:143:6:@W:CG286:@XP_MSG">ip_gddr71tx.v(143)</a><!@TM:1471512135> | Case statement has both a full_case directive and a default clause -- ignoring full_case directive.</font>
Verilog syntax check successful!
Selecting top level module ip_gddr71tx
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\ecp5u.v:367:7:367:10:@N:CG364:@XP_MSG">ecp5u.v(367)</a><!@TM:1471512135> | Synthesizing module INV

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:30:7:30:27:@N:CG364:@XP_MSG">ip_gddr71tx.v(30)</a><!@TM:1471512135> | Synthesizing module ip_gddr71txgddr_sync

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\ecp5u.v:591:7:591:9:@N:CG364:@XP_MSG">ecp5u.v(591)</a><!@TM:1471512135> | Synthesizing module OB

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\ecp5u.v:1658:7:1658:14:@N:CG364:@XP_MSG">ecp5u.v(1658)</a><!@TM:1471512135> | Synthesizing module ODDR71B

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\ecp5u.v:757:7:757:10:@N:CG364:@XP_MSG">ecp5u.v(757)</a><!@TM:1471512135> | Synthesizing module VHI

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\ecp5u.v:168:7:168:14:@N:CG364:@XP_MSG">ecp5u.v(168)</a><!@TM:1471512135> | Synthesizing module FD1S3DX

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\ecp5u.v:761:7:761:10:@N:CG364:@XP_MSG">ecp5u.v(761)</a><!@TM:1471512135> | Synthesizing module VLO

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\ecp5u.v:1534:7:1534:14:@N:CG364:@XP_MSG">ecp5u.v(1534)</a><!@TM:1471512135> | Synthesizing module CLKDIVF

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\lscc\diamond\3.6_x64\cae_library\synthesis\verilog\ecp5u.v:1558:7:1558:16:@N:CG364:@XP_MSG">ecp5u.v(1558)</a><!@TM:1471512135> | Synthesizing module ECLKSYNCB

@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:215:7:215:18:@N:CG364:@XP_MSG">ip_gddr71tx.v(215)</a><!@TM:1471512135> | Synthesizing module ip_gddr71tx

<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:273:8:273:13:@W:CL168:@XP_MSG">ip_gddr71tx.v(273)</a><!@TM:1471512135> | Pruning instance INV_0 -- not in use ...</font>


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 18 17:22:15 2016

###########################################################]
<a name=compilerReport3></a>Synopsys Netlist Linker, version comp201503sp1p1, Build 117R, built Aug 18 2015</a>
@N: : <!@TM:1471512135> | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 18 17:22:15 2016

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 18 17:22:15 2016

###########################################################]
<a name=compilerReport4></a>Synopsys Netlist Linker, version comp201503sp1p1, Build 117R, built Aug 18 2015</a>
@N: : <!@TM:1471512136> | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 18 17:22:16 2016

###########################################################]
Pre-mapping Report

<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1264R, Built Aug 18 2015 10:39:57</a>
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03L-SP1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Reading constraint file: D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.fdc
Linked File: <a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\syn_results\ip_gddr71tx_scck.rpt:@XP_FILE">ip_gddr71tx_scck.rpt</a>
Printing clock  summary report in "D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\syn_results\ip_gddr71tx_scck.rpt" file 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1471512136> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1471512136> | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=56  set on top level netlist ip_gddr71tx

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)



<a name=mapperReport6></a>@S |Clock Summary</a>
*****************

Start                               Requested     Requested     Clock        Clock              
Clock                               Frequency     Period        Type         Group              
------------------------------------------------------------------------------------------------
System                              100.0 MHz     10.000        system       system_clkgroup    
ip_gddr71tx|sclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
ip_gddr71tx|sync_clk                100.0 MHz     10.000        inferred     Inferred_clkgroup_1
================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="d:\bicubicshared\latest\latticefpga\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:303:12:303:25:@W:MT529:@XP_MSG">ip_gddr71tx.v(303)</a><!@TM:1471512136> | Found inferred clock ip_gddr71tx|sclk_inferred_clock which controls 0 sequential elements including Inst4_FD1S3DX. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="d:\bicubicshared\latest\latticefpga\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:95:0:95:6:@W:MT529:@XP_MSG">ip_gddr71tx.v(95)</a><!@TM:1471512136> | Found inferred clock ip_gddr71tx|sync_clk which controls 12 sequential elements including Inst_gddr_sync.cs_gddr_sync[2:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 18 17:22:16 2016

###########################################################]
Map & Optimize Report

<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1264R, Built Aug 18 2015 10:39:57</a>
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03L-SP1

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1471512138> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1471512138> | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		     7.29ns		  23 /        12

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1471512138> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)



<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>

1 non-gated/non-generated clock tree(s) driving 12 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 1 clock pin(s) of sequential element(s)
0 instances converted, 1 sequential instance remains driven by gated/generated clocks

=================================== Non-Gated/Non-Generated Clocks ===================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance               
------------------------------------------------------------------------------------------------------
<a href="@|S:sync_clk@|E:Inst_gddr_sync.cs_gddr_sync[2]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002  @XP_NAMES_BY_PROP">ClockId0002 </a>       sync_clk            port                   12         Inst_gddr_sync.cs_gddr_sync[2]
======================================================================================================
================================================================ Gated/Generated Clocks =================================================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance     Explanation                                                  
---------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|S:Inst2_CLKDIVF@|E:Inst4_FD1S3DX@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       Inst2_CLKDIVF       CLKDIVF                1          Inst4_FD1S3DX       No gated clock conversion method for cell cell:LUCENT.FD1S3DX
=========================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 140MB)

Writing Analyst data base D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\syn_results\synwork\ip_gddr71tx_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)

Writing EDIF Netlist and constraint files
J-2015.03L-SP1
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1471512138> | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

Writing Verilog Simulation files

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

Writing VHDL Simulation files

Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)


Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)

<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\bicubicshared\latest\latticefpga\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:323:14:323:29:@W:MT246:@XP_MSG">ip_gddr71tx.v(323)</a><!@TM:1471512138> | Blackbox ECLKSYNCB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\bicubicshared\latest\latticefpga\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:320:12:320:25:@W:MT246:@XP_MSG">ip_gddr71tx.v(320)</a><!@TM:1471512138> | Blackbox CLKDIVF is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="d:\bicubicshared\latest\latticefpga\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.v:297:12:297:26:@W:MT246:@XP_MSG">ip_gddr71tx.v(297)</a><!@TM:1471512138> | Blackbox ODDR71B is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1471512138> | Found inferred clock ip_gddr71tx|sync_clk with period 10.00ns. Please declare a user-defined clock on object "p:sync_clk"</font> 

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1471512138> | Found inferred clock ip_gddr71tx|sclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:sclk"</font> 



<a name=timingReport9></a>@S |##### START OF TIMING REPORT #####[</a>
# Timing Report written on Thu Aug 18 17:22:18 2016
#


Top view:               ip_gddr71tx
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\ip_gddr71tx.fdc
                       
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1471512138> | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1471512138> | Clock constraints cover only FF-to-FF paths associated with the clock. 



<a name=performanceSummary10></a>Performance Summary </a>
*******************


Worst slack in design: 7.058

@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1471512138> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
                                    Requested     Estimated      Requested     Estimated                Clock        Clock              
Starting Clock                      Frequency     Frequency      Period        Period        Slack      Type         Group              
----------------------------------------------------------------------------------------------------------------------------------------
ip_gddr71tx|sclk_inferred_clock     100.0 MHz     1102.5 MHz     10.000        0.907         9.093      inferred     Inferred_clkgroup_0
ip_gddr71tx|sync_clk                100.0 MHz     339.8 MHz      10.000        2.942         7.058      inferred     Inferred_clkgroup_1
System                              100.0 MHz     NA             10.000        0.000         10.000     system       system_clkgroup    
========================================================================================================================================
@N:<a href="@N:MT582:@XP_HELP">MT582</a> : <!@TM:1471512138> | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack 





<a name=clockRelationships11></a>Clock Relationships</a>
*******************

Clocks                                                 |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------
Starting                         Ending                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------
System                           System                |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
ip_gddr71tx|sclk_inferred_clock  System                |  10.000      9.093   |  No paths    -      |  No paths    -      |  No paths    -    
ip_gddr71tx|sync_clk             System                |  10.000      8.805   |  No paths    -      |  No paths    -      |  No paths    -    
ip_gddr71tx|sync_clk             ip_gddr71tx|sync_clk  |  10.000      7.058   |  No paths    -      |  No paths    -      |  No paths    -    
==============================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo12></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport13></a>Detailed Report for Clock: ip_gddr71tx|sclk_inferred_clock</a>
====================================



<a name=startingSlack14></a>Starting Points with Worst Slack</a>
********************************

                  Starting                                                              Arrival          
Instance          Reference                           Type        Pin     Net           Time        Slack
                  Clock                                                                                  
---------------------------------------------------------------------------------------------------------
Inst4_FD1S3DX     ip_gddr71tx|sclk_inferred_clock     FD1S3DX     Q       preamble1     0.907       9.093
=========================================================================================================


<a name=endingSlack15></a>Ending Points with Worst Slack</a>
******************************

                  Starting                                                              Required          
Instance          Reference                           Type        Pin     Net           Time         Slack
                  Clock                                                                                   
----------------------------------------------------------------------------------------------------------
Inst6_ODDR71B     ip_gddr71tx|sclk_inferred_clock     ODDR71B     D0      preamble1     10.000       9.093
Inst6_ODDR71B     ip_gddr71tx|sclk_inferred_clock     ODDR71B     D1      preamble1     10.000       9.093
==========================================================================================================



<a name=worstPaths16></a>Worst Path Information</a>
<a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\syn_results\ip_gddr71tx.srr:srsfD:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\syn_results\ip_gddr71tx.srs:fp:21942:22188:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      0.907
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 9.093

    Number of logic level(s):                0
    Starting point:                          Inst4_FD1S3DX / Q
    Ending point:                            Inst6_ODDR71B / D0
    The start point is clocked by            ip_gddr71tx|sclk_inferred_clock [rising] on pin CK
    The end   point is clocked by            System [rising]

Instance / Net                 Pin      Pin               Arrival     No. of    
Name               Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
Inst4_FD1S3DX      FD1S3DX     Q        Out     0.907     0.907       -         
preamble1          Net         -        -       -         -           2         
Inst6_ODDR71B      ODDR71B     D0       In      0.000     0.907       -         
================================================================================




====================================
<a name=clockReport17></a>Detailed Report for Clock: ip_gddr71tx|sync_clk</a>
====================================



<a name=startingSlack18></a>Starting Points with Worst Slack</a>
********************************

                                   Starting                                                         Arrival          
Instance                           Reference                Type        Pin     Net                 Time        Slack
                                   Clock                                                                             
---------------------------------------------------------------------------------------------------------------------
Inst_gddr_sync.ctrl_cnt[3]         ip_gddr71tx|sync_clk     FD1S3DX     Q       ctrl_cnt[3]         1.015       7.058
Inst_gddr_sync.ctrl_cnt[0]         ip_gddr71tx|sync_clk     FD1S3DX     Q       ctrl_cnt[0]         1.009       7.064
Inst_gddr_sync.ctrl_cnt[1]         ip_gddr71tx|sync_clk     FD1S3DX     Q       ctrl_cnt[1]         0.985       7.088
Inst_gddr_sync.ctrl_cnt[2]         ip_gddr71tx|sync_clk     FD1S3DX     Q       ctrl_cnt[2]         0.955       7.117
Inst_gddr_sync.cs_gddr_sync[0]     ip_gddr71tx|sync_clk     FD1P3DX     Q       stop                1.027       7.131
Inst_gddr_sync.cs_gddr_sync[1]     ip_gddr71tx|sync_clk     FD1P3DX     Q       cs_gddr_sync[1]     1.015       7.143
Inst_gddr_sync.cs_gddr_sync[2]     ip_gddr71tx|sync_clk     FD1P3DX     Q       ready               1.039       7.771
Inst_gddr_sync.reset_flag          ip_gddr71tx|sync_clk     FD1P3DX     Q       reset_flag          1.015       7.803
Inst_gddr_sync.stop_assert[2]      ip_gddr71tx|sync_clk     FD1S3DX     Q       stop_assert[2]      0.955       7.893
Inst_gddr_sync.stop_assert[0]      ip_gddr71tx|sync_clk     FD1S3DX     Q       stop_assert[0]      0.907       7.941
=====================================================================================================================


<a name=endingSlack19></a>Ending Points with Worst Slack</a>
******************************

                                   Starting                                                               Required          
Instance                           Reference                Type        Pin     Net                       Time         Slack
                                   Clock                                                                                    
----------------------------------------------------------------------------------------------------------------------------
Inst_gddr_sync.reset_flag          ip_gddr71tx|sync_clk     FD1P3DX     SP      reset_flag_1_sqmuxa_i     9.806        7.058
Inst_gddr_sync.ctrl_cnt[0]         ip_gddr71tx|sync_clk     FD1S3DX     D       ctrl_cnt_3[0]             9.946        7.065
Inst_gddr_sync.ctrl_cnt[1]         ip_gddr71tx|sync_clk     FD1S3DX     D       ctrl_cnt_3[1]             9.946        7.065
Inst_gddr_sync.ctrl_cnt[2]         ip_gddr71tx|sync_clk     FD1S3DX     D       ctrl_cnt_3[2]             9.946        7.065
Inst_gddr_sync.ctrl_cnt[3]         ip_gddr71tx|sync_clk     FD1S3DX     D       ctrl_cnt_3[3]             9.946        7.065
Inst_gddr_sync.cs_gddr_sync[0]     ip_gddr71tx|sync_clk     FD1P3DX     D       N_120_i                   9.946        7.197
Inst_gddr_sync.cs_gddr_sync[1]     ip_gddr71tx|sync_clk     FD1P3DX     D       N_131                     9.946        7.803
Inst_gddr_sync.stop_assert[1]      ip_gddr71tx|sync_clk     FD1S3DX     D       stop_assert_4[1]          9.946        7.833
Inst_gddr_sync.stop_assert[2]      ip_gddr71tx|sync_clk     FD1S3DX     D       stop_assert_4[2]          9.946        7.833
Inst_gddr_sync.cs_gddr_sync[2]     ip_gddr71tx|sync_clk     FD1P3DX     D       N_145                     9.946        7.881
============================================================================================================================



<a name=worstPaths20></a>Worst Path Information</a>
<a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\syn_results\ip_gddr71tx.srr:srsfD:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\syn_results\ip_gddr71tx.srs:fp:27403:28687:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.194
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.806

    - Propagation time:                      2.749
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     7.057

    Number of logic level(s):                3
    Starting point:                          Inst_gddr_sync.ctrl_cnt[3] / Q
    Ending point:                            Inst_gddr_sync.reset_flag / SP
    The start point is clocked by            ip_gddr71tx|sync_clk [rising] on pin CK
    The end   point is clocked by            ip_gddr71tx|sync_clk [rising] on pin CK

Instance / Net                                          Pin      Pin               Arrival     No. of    
Name                                       Type         Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------
Inst_gddr_sync.ctrl_cnt[3]                 FD1S3DX      Q        Out     1.015     1.015       -         
ctrl_cnt[3]                                Net          -        -       -         -           6         
Inst_gddr_sync.ns_gddr_sync16              ORCALUT4     D        In      0.000     1.015       -         
Inst_gddr_sync.ns_gddr_sync16              ORCALUT4     Z        Out     0.738     1.753       -         
ns_gddr_sync16                             Net          -        -       -         -           4         
Inst_gddr_sync.ns_gddr_sync_0_sqmuxa_3     ORCALUT4     B        In      0.000     1.753       -         
Inst_gddr_sync.ns_gddr_sync_0_sqmuxa_3     ORCALUT4     Z        Out     0.606     2.359       -         
ns_gddr_sync_0_sqmuxa_3                    Net          -        -       -         -           1         
Inst_gddr_sync.reset_flag_1_sqmuxa_i       ORCALUT4     B        In      0.000     2.359       -         
Inst_gddr_sync.reset_flag_1_sqmuxa_i       ORCALUT4     Z        Out     0.390     2.749       -         
reset_flag_1_sqmuxa_i                      Net          -        -       -         -           1         
Inst_gddr_sync.reset_flag                  FD1P3DX      SP       In      0.000     2.749       -         
=========================================================================================================




====================================
<a name=clockReport21></a>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack22></a>Starting Points with Worst Slack</a>
********************************

                    Starting                                        Arrival           
Instance            Reference     Type          Pin       Net       Time        Slack 
                    Clock                                                             
--------------------------------------------------------------------------------------
Inst1_ECLKSYNCB     System        ECLKSYNCB     ECLKO     eclko     0.000       10.000
======================================================================================


<a name=endingSlack23></a>Ending Points with Worst Slack</a>
******************************

                   Starting                                     Required           
Instance           Reference     Type        Pin      Net       Time         Slack 
                   Clock                                                           
-----------------------------------------------------------------------------------
Inst2_CLKDIVF      System        CLKDIVF     CLKI     eclko     10.000       10.000
Inst5_ODDR71B0     System        ODDR71B     ECLK     eclko     10.000       10.000
Inst5_ODDR71B1     System        ODDR71B     ECLK     eclko     10.000       10.000
Inst5_ODDR71B2     System        ODDR71B     ECLK     eclko     10.000       10.000
Inst5_ODDR71B3     System        ODDR71B     ECLK     eclko     10.000       10.000
Inst6_ODDR71B      System        ODDR71B     ECLK     eclko     10.000       10.000
===================================================================================



<a name=worstPaths24></a>Worst Path Information</a>
<a href="D:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\syn_results\ip_gddr71tx.srr:srsfD:\BicubicShared\Latest\LatticeFPGA\ecp5_lvds\ip_gddr71tx\syn_results\ip_gddr71tx.srs:fp:31680:31938:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      0.000
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 10.000

    Number of logic level(s):                0
    Starting point:                          Inst1_ECLKSYNCB / ECLKO
    Ending point:                            Inst2_CLKDIVF / CLKI
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                    Pin       Pin               Arrival     No. of    
Name                Type          Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
Inst1_ECLKSYNCB     ECLKSYNCB     ECLKO     Out     0.000     0.000       -         
eclko               Net           -         -       -         -           6         
Inst2_CLKDIVF       CLKDIVF       CLKI      In      0.000     0.000       -         
====================================================================================



##### END OF TIMING REPORT #####]


Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)


Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 143MB)

---------------------------------------
<a name=resourceUsage25></a>Resource Usage Report</a>
Part: lfe5u_25f-6

Register bits: 13 of 24288 (0%)
PIC Latch:       0
I/O cells:       5


Details:
FD1P3DX:        4
FD1S3BX:        1
FD1S3DX:        8
GSR:            1
INV:            1
OB:             5
ORCALUT4:       22
PUR:            1
VHI:            2
VLO:            2
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 53MB peak: 143MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 18 17:22:18 2016

###########################################################]

</pre></samp></body></html>
